Reducing Data Bottlenecks in Distributed, Heterogeneous Neural Networks
Ruhai Lin, Rui-Jie Zhu, Jason K. Eshraghian

TL;DR
This paper explores how reducing data traffic in distributed neural networks on embedded systems impacts performance, proposing a co-design approach with narrow layers to balance data transfer and accuracy.
Contribution
It introduces a hardware-software co-design method replacing data bottlenecks with learnable embeddings to minimize data transfer in neural networks.
Findings
Higher bottleneck ratios decrease data transfer volume.
Shallower models are more sensitive to bottleneck increases.
Trade-offs between accuracy and data transfer volume are characterized.
Abstract
The rapid advancement of embedded multicore and many-core systems has revolutionized computing, enabling the development of high-performance, energy-efficient solutions for a wide range of applications. As models scale up in size, data movement is increasingly the bottleneck to performance. This movement of data can exist between processor and memory, or between cores and chips. This paper investigates the impact of bottleneck size, in terms of inter-chip data traffic, on the performance of deep learning models in embedded multicore and many-core systems. We conduct a systematic analysis of the relationship between bottleneck size, computational resource utilization, and model accuracy. We apply a hardware-software co-design methodology where data bottlenecks are replaced with extremely narrow layers to reduce the amount of data traffic. In effect, time-multiplexing of signals is…
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Taxonomy
TopicsNeural Networks and Applications
