Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning

TL;DR

This paper introduces a 3nm FinFET SRAM-based CIM architecture optimized for SNN inference, achieving significant improvements in speed and energy efficiency suitable for edge devices.

Contribution

It presents a novel multiport SRAM design with online learning capabilities for SNNs, enhancing throughput and energy efficiency over traditional designs.

Findings

3.1× speed improvement over single-port SRAM

2.2× energy efficiency enhancement

Achieves 44 MInf/s throughput at 607 pJ/Inf

Abstract

Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones, wearables, and Internet-of-Things sensor systems. In this paper, we propose a new SRAM-based Compute-In-Memory (CIM) accelerator optimized for Spiking Neural Networks (SNNs) Inference. Our proposed architecture employs a multiport SRAM design with multiple decoupled Read ports to enhance the throughput and Transposable Read-Write ports to facilitate online learning. Furthermore, we develop an Arbiter circuit for efficient data-processing and port allocations during the computation. Results for a 128$\times$128 array in 3nm FinFET technology demonstrate a 3.1$\times$ improvement in speed and a 2.2$\times$ enhancement in energy efficiency with our proposed multiport SRAM design compared to the traditional single-port design. At system-level, a throughput of 44 MInf/s at 607 pJ/Inf and 29mW is achieved.