RISC-V V Vector Extension (RVV) with reduced number of vector registers

TL;DR

This paper proposes reducing the number of vector registers in RISC-V's RVV extension from 32 to 8 or 16 to save area, while maintaining most features and compatibility through compiler parameterization.

Contribution

It introduces a simplified RVV extension with fewer registers, enabling smaller, efficient processors without full binary compatibility but with adaptable compiler support.

Findings

Reduced register count saves area in small processors.

High utilization of vector cores is maintained with fewer registers.

Signal processing kernels benefit from the reduced register configuration.

Abstract

To reduce the area of RISC-V Vector extension (RVV) in small processors, the authors are considering one simple modification: reduce the number of registers in the vector register file. The standard 'V' extension requires 32 vector registers that we propose to reduce to 16 or 8 registers. Other features of RVV are still supported. Reducing the number of vector registers does not generate a completely new programming model: although the resulting core does not have binary code compatibility with standard RVV, compiling for it just requires parameterization of the vector register file size in the compiler. The reduced vector register file allows for still high utilization of vector RVV processor core. Many useful signal processing kernels require few registers, and become efficient at 1:4 chaining ratio.