Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core

TL;DR

This paper investigates how dynamic hardware approximation techniques can improve energy efficiency in a RISC-V embedded processor, achieving significant power savings and performance trade-offs in a 45nm CMOS technology.

Contribution

It introduces a specialized RISC-V platform with hardware approximation features and evaluates its energy efficiency improvements over accurate computation.

Findings

Average energy efficiency of 13.3 pJ/instruction at 500MHz

9.21% overall energy efficiency improvement

Significant reduction in multiplication instruction energy consumption

Abstract

The limited energy available in most embedded systems poses a significant challenge in enhancing the performance of embedded processors and microcontrollers. One promising approach to address this challenge is the use of approximate computing, which can be implemented in both hardware and software layers to balance the trade-off between performance and power consumption. In this study, the impact of dynamic hardware approximation methods on the run-time energy efficiency of a RISC-V embedded processor with specialized features for approximate computing is investigated. The results indicate that the platform achieves an average energy efficiency of 13.3 pJ/instruction at a 500MHz clock frequency adhering approximation in 45nm CMOS technology. Compared to accurate circuits and computation, the approximate computing techniques in the processing core resulted in a significant improvement of 9.21% in overall energy efficiency, 60.83% in multiplication instructions, 14.64% in execution stage, and 9.23% in overall power consumption.