Limited Parallelization in Gate Operations Leads to Higher Space Overhead and Lower Noise Threshold
Sai Sanjay Narayanan, Smita Bagewadi, Avhishek Chatterjee

TL;DR
This paper demonstrates that limited gate parallelization in quantum error correction significantly increases space overhead and reduces noise thresholds, highlighting the importance of parallel operations for fault-tolerance.
Contribution
It provides an analytical lower bound on space overhead related to gate parallelization, showing increased costs when parallelism is restricted.
Findings
Lower bounds on space overhead are strictly larger with limited parallelization.
Noise threshold vanishes if parallel gate operations do not scale linearly with qubits.
Limited parallelization leads to higher decoherence and error rates.
Abstract
In a modern error corrected quantum memory or circuit, parallelization of gate operations is severely restricted due to issues like cross-talk. Hence, there are enough idle qubits not undergoing gate operations either during the computation phase or during the error correction phase, which suffer further decoherence while waiting. Thus, in reality, the space overhead and the noise threshold would depend on the level of gate parallelization. In this paper, we obtain an analytical lower bound on the required space overhead in terms of the level of parallelization for an error correction framework that has more error correction capability than the existing ones. We consider two types of errors: i.i.d. erasure and depolarization. In comparison to the known lower bounds which assume full gate parallelization, our bound is provably strictly larger despite allowing more capability to the error…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsSemiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Low-power high-performance VLSI design
