Intelligent Pixel Detectors: Towards a Radiation Hard ASIC with On-Chip Machine Learning in 28 nm CMOS

TL;DR

This paper presents the development of a radiation-hard CMOS ASIC with integrated machine learning for intelligent pixel detectors, aiming to enable fast, power-efficient data reduction at high event rates in future collider experiments.

Contribution

It introduces a novel 28nm CMOS readout chip with on-chip neural network processing for particle tracking in high-energy physics detectors.

Findings

Successful hardware implementation of neural network for track prediction

Feasibility of real-time data reduction at 40 MHz

Preliminary results show promising performance for particle feature extraction

Abstract

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. We are developing a radiation hard readout integrated circuit (ROIC) in 28nm CMOS with on-chip machine learning (ML) for future intelligent pixel detectors. We will show track parameter predictions using a neural network within a single layer of silicon and hardware tests on the first tape-outs produced with TSMC. Preliminary results indicate that reading out featurized clusters from particles above a modest momentum threshold could enable using pixel information at 40 MHz.