Using a Performance Model to Implement a Superscalar CVA6

TL;DR

This paper presents a performance model for the CVA6 RISC-V processor that accurately predicts performance and aids in evaluating and optimizing a superscalar feature, leading to significant performance gains.

Contribution

It introduces a high-accuracy performance model for CVA6 that facilitates design evaluation and bug detection before RTL implementation, and demonstrates the effectiveness of a superscalar feature.

Findings

Performance model accuracy of 99.2% on CoreMark

40% performance improvement with superscalar feature

Model helped detect and fix performance bugs

Abstract

A performance model of CVA6 RISC-V processor is built to evaluate performance related modifications before implementing them in RTL. Its accuracy is 99.2% on CoreMark. This model is used to evaluate a superscalar feature for CVA6. During design phase, the model helped detecting and fixing performance bugs. The superscalar feature resulted in a CVA6 performance improvement of 40% on CoreMark.