Design and In-training Optimization of Binary Search ADC for Flexible Classifiers

TL;DR

This paper introduces a Binary Search ADC design optimized for flexible electronics, significantly reducing area and power consumption while maintaining classifier accuracy, enabling efficient analog-to-digital interfacing in low-cost, flexible devices.

Contribution

It presents a novel Binary Search ADC design with reduced area overhead and an in-training optimization method that simplifies ADCs, lowering area by up to 5X with minimal accuracy loss.

Findings

Binary Search ADC reduces area by 2X compared to previous designs.

In-training optimization cuts ADC transistor count by 5X with <1% accuracy loss.

Proposed methods enable efficient, low-cost analog-to-digital conversion for flexible electronics.

Abstract

Flexible Electronics (FE) offer distinct advantages, including mechanical flexibility and low process temperatures, enabling extremely low-cost production. To address the demands of applications such as smart sensors and wearables, flexible devices must be small and operate at low supply voltages. Additionally, target applications often require classifiers to operate directly on analog sensory input, necessitating the use of Analog to Digital Converters (ADCs) to process the sensory data. However, ADCs present serious challenges, particularly in terms of high area and power consumption, especially when considering stringent area and energy budget. In this work, we target common classifiers in this domain such as MLPs and SVMs and present a holistic approach to mitigate the elevated overhead of analog to digital interfacing in FE. First, we propose a novel design for Binary Search ADC that reduces area overhead 2X compared with the state-of-the-art Binary design and up to 5.4X compared with Flash ADC. Next, we present an in-training ADC optimization in which we keep the bare-minimum representations required and simplifying ADCs by removing unnecessary components. Our in-training optimization further reduces on average the area in terms of transistor count of the required ADCs by 5X for less than 1% accuracy loss.