A Scheduling-Aware Defense Against Prefetching-Based Side-Channel Attacks
Till Schl\"uter, Nils Ole Tippenhauer

TL;DR
This paper introduces PreFence, a scheduling-aware defense mechanism that temporarily disables CPU prefetchers during security-critical operations to prevent prefetch-based side-channel attacks, with minimal performance impact.
Contribution
The work systematizes prefetch-based side-channel vulnerabilities and presents PreFence, a novel, adaptable countermeasure for x86_64 and ARM processors that effectively mitigates these attacks.
Findings
PreFence reliably stops prefetch leakage.
Negligible performance impact during security-critical operations.
Effective on x86_64 and ARM architectures.
Abstract
Modern computer processors use microarchitectural optimization mechanisms to improve performance. As a downside, such optimizations are prone to introducing side-channel vulnerabilities. Speculative loading of memory, called prefetching, is common in real-world CPUs and may cause such side-channel vulnerabilities: Prior work has shown that it can be exploited to bypass process isolation and leak secrets, such as keys used in RSA, AES, and ECDH implementations. However, to this date, no effective and efficient countermeasure has been presented that secures software on systems with affected prefetchers. In this work, we answer the question: How can a process defend against prefetch-based side channels? We first systematize prefetching-based side-channel vulnerabilities presented in academic literature so far. Next, we design and implement PreFence, a scheduling-aware defense against…
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Taxonomy
TopicsCryptographic Implementations and Security · Coding theory and cryptography · Chaos-based Image/Signal Encryption
