FastFlow in FPGA Stacks of Data Centers

TL;DR

This paper introduces an extension of FastFlow that simplifies programming FPGA stacks in data centers by automatically generating host-side code from CSV files, significantly reducing coding effort and improving scalability.

Contribution

It presents a novel tool flow integrating FastFlow with Vitis to automate FPGA stack programming, making high-level parallel programming more accessible and efficient.

Findings

Reduces 96% of coding effort compared to existing solutions

Enables automatic host code generation from simple CSV parameters

Improves scalability and efficiency of FPGA stack programming

Abstract

FPGA programming is more complex as compared to Central Processing Units (CPUs) and Graphics Processing Units (GPUs). The coding languages to define the abstraction of Register Transfer Level (RTL) in High Level Synthesis (HLS) for FPGA platforms have emerged due to the laborious complexity of Hardware Description Languages (HDL). The HDL and High Level Synthesis (HLS) became complex when FPGA is adopted in high-performance parallel programs in multicore platforms of data centers. Writing an efficient host-side parallel program to control the hardware kernels placed in stacks of FPGAs is challenging and strenuous. The unavailability of efficient high level parallel programming tools for multi core architectures makes multicore parallel programming very unpopular for the masses. This work proposes an extension of FastFlow where data flows in hardware kernels can be executed efficiently in FPGA stacks. Here host side codes are generated automatically from simple csv files. The programmer needs to specify four simple parameters in these csv file: FPGA IDs, source, destination nodes, hardware kernel names. The proposed tool flow uses FastFlow libraries with Vitis to develop efficient and scalable parallel programs for FPGA stacks in data centers. The evidence from the implementation shows that the integration of FastFlow with Vitis reduces 96 % coding effort (in terms of number of lines) as compared to existing Vitis solutions.