RNC: Efficient RRAM-aware NAS and Compilation for DNNs on Resource-Constrained Edge Devices

TL;DR

This paper introduces an RRAM-aware neural architecture search and compilation framework tailored for resource-constrained edge devices, significantly improving neural network efficiency and speed on resistive memory-based accelerators.

Contribution

It proposes a novel edge compilation and NAS framework that optimizes DNNs for RRAM-based accelerators under hardware constraints, enhancing utilization and speed.

Findings

Over 80% hardware utilization achieved.

Over 6x speedup compared to baseline frameworks.

Speed improvements of 5x-30x for optimized models.

Abstract

Computing-in-memory (CIM) is an emerging computing paradigm, offering noteworthy potential for accelerating neural networks with high parallelism, low latency, and energy efficiency compared to conventional von Neumann architectures. However, existing research has primarily focused on hardware architecture and network co-design for large-scale neural networks, without considering resource constraints. In this study, we aim to develop edge-friendly deep neural networks (DNNs) for accelerators based on resistive random-access memory (RRAM). To achieve this, we propose an edge compilation and resource-constrained RRAM-aware neural architecture search (NAS) framework to search for optimized neural networks meeting specific hardware constraints. Our compilation approach integrates layer partitioning, duplication, and network packing to maximize the utilization of computation units. The resulting network architecture can be optimized for either high accuracy or low latency using a one-shot neural network approach with Pareto optimality achieved through the Non-dominated Sorted Genetic Algorithm II (NSGA-II). The compilation of mobile-friendly networks, like Squeezenet and MobilenetV3 small can achieve over 80% of utilization and over 6x speedup compared to ISAAC-like framework with different crossbar resources. The resulting model from NAS optimized for speed achieved 5x-30x speedup. The code for this paper is available at https://github.com/ArChiiii/rram_nas_comp_pack.