PhD Forum: Efficient Privacy-Preserving Processing via Memory-Centric Computing

TL;DR

This paper introduces a framework leveraging memory-centric processing-in-memory hardware to significantly improve the efficiency of privacy-preserving computations like homomorphic encryption and secure multi-party computation by reducing data movement and exploiting parallelism.

Contribution

It presents a novel four-layer architecture that integrates PIM hardware with secure computation protocols, addressing the data transfer bottleneck in privacy-preserving processing.

Findings

Reduces data transfer overhead using data compression techniques.

Achieves significant performance improvements over traditional approaches.

Integrates PIM hardware with existing cryptographic protocols effectively.

Abstract

Privacy-preserving computation techniques like homomorphic encryption (HE) and secure multi-party computation (SMPC) enhance data security by enabling processing on encrypted data. However, the significant computational and CPU-DRAM data movement overhead resulting from the underlying cryptographic algorithms impedes the adoption of these techniques in practice. Existing approaches focus on improving computational overhead using specialized hardware like GPUs and FPGAs, but these methods still suffer from the same processor-DRAM overhead. Novel hardware technologies that support in-memory processing have the potential to address this problem. Memory-centric computing, or processing-in-memory (PIM), brings computation closer to data by introducing low-power processors called data processing units (DPUs) into memory. Besides its in-memory computation capability, PIM provides extensive parallelism, resulting in significant performance improvement over state-of-the-art approaches. We propose a framework that uses recently available PIM hardware to achieve efficient privacy-preserving computation. Our design consists of a four-layer architecture: (1) an application layer that decouples privacy-preserving applications from the underlying protocols and hardware; (2) a protocol layer that implements existing secure computation protocols (HE and MPC); (3) a data orchestration layer that leverages data compression techniques to mitigate the data transfer overhead between DPUs and host memory; (4) a computation layer which implements DPU kernels on which secure computation algorithms are built.