Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations

TL;DR

This paper introduces a high-speed 16-bit binary multiplier design using reformed array logic, multiplexers, barrel shifters, and combined carry save and ripple carry adders, demonstrated on Cadence Virtuoso.

Contribution

A novel multiplier architecture that enhances speed by integrating reformed array logic with multiplexers, barrel shifters, and combined adder techniques.

Findings

Achieved faster multiplication using combined CSA and RCA.

Demonstrated scalable design for different bit-widths.

Validated performance on Cadence Virtuoso.

Abstract

Binary multipliers have long been a staple component in digital circuitry, serving crucial roles in microprocessor design, digital signal processing units and many more applications. This work presents a unique design for a multiplier that utilizes a reformed-array-logic approach to compute the product of two unsigned binary numbers. We employed a multiplexer and a barrel shifter to multiply partial products in a single clock cycle to speed up the traditional array logic. In addition, we have employed a combination of Carry Save Adders (CSA) and Ripple Carry Adders (RCA) to accumulate the partial products instead of using standalone RCAs to speed up the multiplication process further. Finally, we have demonstrated our design to perform multiplication of two 16-bit unsigned binary numbers on Cadence Virtuoso. Our design is modular and can be scaled up or down to accommodate the multiplication of any n-bit unsigned numbers.