Deep Circuit Compression for Quantum Dynamics via Tensor Networks

TL;DR

This paper introduces a tensor network-based compilation algorithm that compresses quantum circuits, enabling more accurate and shallower simulations on near-term quantum hardware, demonstrated on up to 64-layer circuits and a 52-qubit 2D topology.

Contribution

The authors develop a scalable matrix product operator-based method for circuit compression that outperforms traditional Trotterization in accuracy and depth reduction.

Findings

Achieved circuit compression with over 6-fold depth reduction.

Produced circuits with up to 4 orders of magnitude lower error.

Successfully compiled a 52-qubit 2D Transverse-Field Ising model.

Abstract

Dynamic quantum simulation is a leading application for achieving quantum advantage. However, high circuit depths remain a limiting factor on near-term quantum hardware. We present a compilation algorithm based on Matrix Product Operators for generating compressed circuits enabling real-time simulation on digital quantum computers, that for a given depth are more accurate than all Trotterizations of the same depth. By the efficient use of environment tensors, the algorithm is scalable in depth beyond prior work, and we present circuit compilations of up to 64 layers of $SU(4)$ gates. Surpassing only 1D circuits, our approach can flexibly target a particular quasi-2D gate topology. We demonstrate this by compiling a 52-qubit 2D Transverse-Field Ising propagator onto the IBM Heavy-Hex topology. For all circuit depths and widths tested, we produce circuits with smaller errors than all equivalent depth Trotter unitaries, corresponding to reductions in error by up to 4 orders of magnitude and circuit depth compressions with a factor of over 6.