A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping

TL;DR

This paper presents a high-speed 3.5 GS/s MASH VCO ADC in 28nm CMOS with second-order noise shaping, achieving high SNDR and DR with low power consumption and small area.

Contribution

It introduces a scalable open-loop MASH VCO ADC with multi-bit error estimation enabling high bandwidth and second-order noise shaping in 28nm CMOS.

Findings

Achieves 67 dB SNDR at 109.375 MHz bandwidth.

Consumes 9 mW analog and 24 mW digital power.

Core area of 0.017 mm^2 with FoM_DR of 163 dB.

Abstract

In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop configuration. A key enabler of the high-bandwidth MASH VCO ADC is the use of a multi-bit estimated error signal. With an OSR of 16, an SNDR of 67 dB and DR of 68 dB are achieved in 109.375 MHz bandwidth. The full-custom pseudo-analog circuits consume 9 mW, while the automatically generated digital circuits consume another 24 mW. A $\mathbf{FoM_{DR} = 163}$ dB and core area of $\mathbf{0.017\,\mathbf{mm}^2}$ are obtained.