TCAD Simulation of Novel Multi-Spacer HK/MG 28nm Planar MOSFET for Sub-threshold Swing and DIBL Optimization

TL;DR

This paper uses TCAD simulations to optimize a novel 28 nm planar MOSFET design with multi-spacers and high-k metal-gate to improve subthreshold swing and reduce DIBL, leading to lower power consumption.

Contribution

It introduces a new 28 nm MOSFET structure with multi-spacers and high-k gate, demonstrating improved subthreshold swing and DIBL mitigation through simulation.

Findings

Lower subthreshold swing of 69.8 mV/dec.

Reduced DIBL effect to 30.5 mV/V.

Enhanced device performance over existing 28 nm MOSFETs.

Abstract

This study optimizes 28 nm planar MOSFET technology to reduce device leakage current and enhance switching speed. The specific aims are to decrease subthreshold swing (S.S.) and mitigate drain induced barrier lowering (DIBL) effect. Silvaco TCAD software is used for process (Athena) and device (Atlas) simulations. For the further development of MOSFET technology, we implemented our device (planar 28 nm n-MOSFET) with high-k metal-gate (HK/MG), lightly doped drain (LDD), multiple spacers (mult-spacers), and silicide. Simulation validation shows improvements over other 28 nm devices, with lower static power consumption and notable optimizations in both S.S. (69.8 mV/dec) and DIBL effect (30.5 mV/V).