Analogous Alignments: Digital "Formally" meets Analog
Hansa Mohanty, Deepak Narayan Gadde

TL;DR
This paper presents a novel formal verification approach for mixed-signal IPs, integrating analog behavioral models into digital verification to improve early bug detection and verification efficiency.
Contribution
It introduces 'Analogous Alignments', a method for seamlessly incorporating analog models into formal digital verification setups, addressing compatibility and complexity challenges.
Findings
Successfully verified mixed-signal IPs with early bug detection.
Mitigated state-space explosion using k-induction techniques.
Achieved comprehensive verification within reasonable timeframes.
Abstract
The complexity of modern-day System-on-Chips (SoCs) is continually increasing, and it becomes increasingly challenging to deliver dependable and credible chips in a short time-to-market. Especially, in the case of test chips, where the aim is to study the feasibility of the design, time is a crucial factor. Pre-silicon functional verification is one of the main contributors that makes up a large portion of the product development cycle. Verification engineers often loosely verify test chips that turn out to be non-functional on the silicon, ultimately resulting in expensive re-spins. To left-shift the verification efforts, formal verification is a powerful methodology that aims to exhaustively verify designs, giving better confidence in the overall quality. This paper focuses on the pragmatic formal verification of a mixed signal Intellectual Property (IP) that has a combination of…
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Taxonomy
TopicsArchitecture and Computational Design · Manufacturing Process and Optimization
