MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs

TL;DR

This paper introduces MESC, a system enabling fine-grained instruction-level preemption in heterogeneous MCSs, significantly reducing priority inversions and improving real-time predictability without workload modifications.

Contribution

We propose a novel instruction-level preemption method for DNN accelerators, enabling fine-grained context switching to address priority inversions in heterogeneous MCSs.

Findings

250x speedup in resolving priority inversions

300x speedup in criticality inversions

Less than 5% overhead

Abstract

Modern Mixed-Criticality Systems (MCSs) rely on hardware heterogeneity to satisfy ever-increasing computational demands. However, most of the heterogeneous co-processors are designed to achieve high throughput, with their micro-architectures executing the workloads in a streaming manner. This streaming execution is often non-preemptive or limited-preemptive, preventing tasks' prioritisation based on their importance and resulting in frequent occurrences of algorithmic priority and/or criticality inversions. Such problems present a significant barrier to guaranteeing the systems' real-time predictability, especially when co-processors dominate the execution of the workloads (e.g., DNNs and transformers). In contrast to existing works that typically enable coarse-grained context switch by splitting the workloads/algorithms, we demonstrate a method that provides fine-grained context switch on a widely used open-source DNN accelerator by enabling instruction-level preemption without any workloads/algorithms modifications. As a systematic solution, we build a real system, i.e., Make Each Switch Count (MESC), from the SoC and ISA to the OS kernel. A theoretical model and analysis are also provided for timing guarantees. Experimental results reveal that, compared to conventional MCSs using non-preemptive DNN accelerators, MESC achieved a 250x and 300x speedup in resolving algorithmic priority and criticality inversions, with less than 5\% overhead. To our knowledge, this is the first work investigating algorithmic priority and criticality inversions for MCSs at the instruction level.