Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness

TL;DR

This paper introduces a hardware/algorithm co-design for real-time I/O control that enhances timing accuracy and robustness in safety-critical systems through a novel ETS-based scheduling approach.

Contribution

It proposes a robust I/O co-processor with Execution Time Servers and a two-level scheduler to improve timing accuracy and defect resilience.

Findings

Outperforms state-of-the-art in timing accuracy

Enhances robustness against timing defects

Maintains low overhead

Abstract

In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been investigated and developed. However, these solutions are often fragile, due to unforeseen timing defects. In this paper, we propose a robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler. The ETSs limit the impact of timing defects between tasks, and the scheduler prioritises ETSs based on their importance, offering a robust and configurable scheduling infrastructure. Based on the hardware design, we present an ETS-based timing-accurate I/O schedule, with the ETS parameters configured to further enhance robustness against timing defects. Experiments show the proposed I/O control method outperforms the state-of-the-art method in terms of timing accuracy and robustness without introducing significant overhead.