Hardware-efficient quantum error correction via concatenated bosonic qubits
Harald Putterman, Kyungjoo Noh, Connor T. Hann, Gregory S. MacCabe,, Shahriar Aghaeimeibodi, Rishi N. Patel, Menyoung Lee, William M. Jones, Hesam, Moradinejad, Roberto Rodriguez, Neha Mahuli, Jefferson Rose, John Clai Owens,, Harry Levine, Emma Rosenfeld, Philip Reinhold

TL;DR
This paper demonstrates a hardware-efficient quantum error correction method using concatenated bosonic cat qubits and a repetition code, achieving significant suppression of logical errors in a superconducting circuit.
Contribution
It introduces a practical implementation of concatenated bosonic qubits with an outer repetition code, showing improved error suppression and scalability for fault-tolerant quantum computing.
Findings
Logical phase-flip error decreases with code distance from 3 to 5
Logical bit-flip error is suppressed with higher photon number
Minimum logical error per cycle around 1.7% for distance-3 and 1.65% for distance-5
Abstract
In order to solve problems of practical importance, quantum computers will likely need to incorporate quantum error correction, where a logical qubit is redundantly encoded in many noisy physical qubits. The large physical-qubit overhead typically associated with error correction motivates the search for more hardware-efficient approaches. Here, using a microfabricated superconducting quantum circuit, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance . The bosonic cat qubits are passively protected against bit flips using a stabilizing circuit. Cat-qubit phase-flip errors are corrected by the repetition code which uses ancilla transmons for syndrome measurement. We realize a noise-biased CX gate which ensures bit-flip error suppression is maintained during error correction. We study the…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum and electron transport phenomena · Quantum Information and Cryptography
