Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons
Nanako Kimura, Ckristian Duran, Zolboo Byambadorj, Ryosho Nakane, and Tetsuya Iizuka

TL;DR
This paper presents a CMOS-based analog spiking neuron leveraging time-domain signals for hardware-efficient reservoir computing, demonstrating high accuracy in temporal tasks and simplified hardware design.
Contribution
It introduces a novel CMOS-compatible spiking neuron design using time-domain signals and a simple network structure for practical physical reservoir computing applications.
Findings
Achieved 97.7% accuracy in spoken digit recognition.
Demonstrated effective short-term memory and XOR tasks.
Provided a hardware-friendly, scalable neuron implementation.
Abstract
This paper introduces an analog spiking neuron that utilizes time-domain information, i.e., a time interval of two signal transitions and a pulse width, to construct a spiking neural network (SNN) for a hardware-friendly physical reservoir computing (RC) on a complementary metal-oxide-semiconductor (CMOS) platform. A neuron with leaky integrate-and-fire is realized by employing two voltage-controlled oscillators (VCOs) with opposite sensitivities to the internal control voltage, and the neuron connection structure is restricted by the use of only 4 neighboring neurons on the 2-dimensional plane to feasibly construct a regular network topology. Such a system enables us to compose an SNN with a counter-based readout circuit, which simplifies the hardware implementation of the SNN. Moreover, another technical advantage thanks to the bottom-up integration is the capability of dynamically…
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Taxonomy
TopicsNeural Networks and Reservoir Computing · Advanced Memory and Neural Computing · Neural Networks and Applications
MethodsSpiking Neural Networks
