Micro-orchestration of RAN functions accelerated in FPGA SoC devices

TL;DR

This paper proposes a hierarchical, data-driven micro-orchestration framework for FPGA SoC devices to improve resource utilization in 5G and edge computing, enabling dynamic function management based on context.

Contribution

It introduces a resource management layer and a micro-orchestrator design for FPGA SoC devices, tailored for RAN function lifecycle management in 5G networks.

Findings

Framework enables dynamic migration and scaling of functions.

Supports context-aware resource management.

Lays foundation for RAN-specific micro-orchestration in O-RAN.

Abstract

This work provides a vision on how to tackle the underutilization of compute resources in FPGA SoC devices used across 5G and edge computing infrastructures. A first step towards this end is the implementation of a resource management layer able to migrate and scale functions in such devices, based on context events. This layer sets the basis to design a hierarchical data-driven micro-orchestrator in charge of providing the lifecycle management of functions in FPGA SoC devices. In the O-RAN context, the micro-orchestrator is foreseen to take the form of an xApp/rApp tandem trained with RAN traffic and context data.