Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects

TL;DR

This paper challenges traditional DMA-based I/O interfaces, proposing that programmed I/O with cache-coherent interconnects can offer lower latency and competitive throughput for modern workloads and hardware architectures.

Contribution

It demonstrates in hardware that cache-coherent programmed I/O can outperform DMA in latency and match throughput, with practical use-cases for microservices and serverless computing.

Findings

Cache-coherent programmed I/O reduces latency in fine-grained communication.

Throughput of programmed I/O is competitive with DMA over modern interconnects.

Practical implementations show benefits in microservice and serverless workloads.

Abstract

Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should use Direct Memory Access (DMA) to offload data transfer, descriptor rings for buffering and queuing, and interrupts for asynchrony between cores and device. In this paper we question this wisdom in the light of two trends: modern and emerging cache-coherent interconnects like CXL3.0, and workloads, particularly microservices and serverless computing. Like some others before us, we argue that the assumptions of the DMA-based model are obsolete, and in many use-cases programmed I/O, where the CPU explicitly transfers data and control information to and from a device via loads and stores, delivers a more efficient system. However, we push this idea much further. We show, in a real hardware implementation, the gains in latency for fine-grained communication achievable using an open cache-coherence protocol which exposes cache transitions to a smart device, and that throughput is competitive with DMA over modern interconnects. We also demonstrate three use-cases: fine-grained RPC-style invocation of functions on an accelerator, offloading of operators in a streaming dataflow engine, and a network interface targeting serverless functions, comparing our use of coherence with both traditional DMA-style interaction and a highly-optimized implementation using memory-mapped programmed I/O over PCIe.