High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform

TL;DR

This paper demonstrates a high-performance three-terminal thyristor RAM on a silicon photonic CMOS platform, utilizing a novel doping profile to enhance memory performance and employing TCAD modeling for analysis.

Contribution

Introduces a new P+PNPNN+ doping profile for 3T TRAM on silicon photonics, achieving improved memory performance over conventional structures.

Findings

Experimental validation of the 3T TRAM with new doping profile

Enhanced memory performance compared to traditional designs

Modeling confirms physical behavior and high-speed operation

Abstract

3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a silicon photonic platform. By using additional implant layers, this device provides excellent memory performance compared to the conventional structure (PNPN). TCAD is used to reflect the physical behavior, and the high-speed memory operations are described through the model.