fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning

TL;DR

This paper introduces fence.t.s, a software-supported temporal partitioning method that effectively closes timing channels in high-performance out-of-order cores with minimal hardware costs and performance impact.

Contribution

It proposes a novel fence.t.s mechanism that extends ISA support for microarchitectural timing channel mitigation in out-of-order processors.

Findings

Achieves full timing channel protection in out-of-order cores

Imposes only 1.0% performance overhead

Requires negligible hardware modifications

Abstract

Microarchitectural timing channels exploit information leakage between security domains that should be isolated, bypassing the operating system's security boundaries. These channels result from contention for shared microarchitectural state. In the RISC-V instruction set, the temporal fence instruction (fence.t) was proposed to close timing channels by providing an operating system with the means to temporally partition microarchitectural state inexpensively in simple in-order cores. This work explores challenges with fence.t in superscalar out-of-order cores featuring large and pervasive microarchitectural state. To overcome these challenges, we propose a novel SW-supported temporal fence (fence.t.s), which reuses existing mechanisms and supports advanced microarchitectural features, enabling full timing channel protection of an exemplary out-of-order core (OpenC910) at negligible hardware costs and a minimal performance impact of 1.0 %.