Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge

TL;DR

This paper presents an FPGA-based solution using P4 and High-Level Synthesis to extract TCP/IP headers at 95 Gbps, enabling real-time anonymized traffic analysis for high-speed networks.

Contribution

It introduces the first integration of P4 and HLS on AMD FPGAs for high-speed packet processing, achieving 95 Gbps throughput.

Findings

Achieved 95 Gbps processing rate with FPGA implementation.

Successfully extracted IP address information from 100 Gbps network traffic.

Demonstrated the feasibility of combining P4 and HLS for high-speed network functions.

Abstract

Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network researchers can create customized FPGA-based network functions and execute network tasks on accelerators directly connected to the network. A feature of the P4 language is that it is stateless; however, the FPGA implementation in this research requires state information. This is accomplished using P4 externs to describe the stateful portions of the design and to implement them on the FPGA using High-Level Synthesis (HLS). This paper demonstrates using an FPGA-based SmartNIC to efficiently extract source-destination IP address information from network packets and construct anonymized network traffic matrices for further analysis. The implementation is the first example of the combination of using P4 and HLS in developing network functions on the latest AMD FPGAs. Our design achieves a processing rate of approximately 95 Gbps with the combined use of P4 and High-level Synthesis and is able to keep up with 100 Gbps traffic received directly from the network.