Delay-Optimum Adder Circuits with Linear Size

TL;DR

This paper introduces delay-optimized binary adder circuits that achieve minimal delay with linear size, improving efficiency by considering input arrival times and providing the fastest known circuits under these constraints.

Contribution

It presents the first linear-size adder circuits optimized for delay with input arrival time considerations, including the fastest sub-quadratic and linear size adders.

Findings

Achieved linear size adder circuits with delay close to the lower bound

Developed fastest sub-quadratic size adder circuits

Provided a delay formula involving input arrival times and logarithmic factors

Abstract

We present efficient circuits for the addition of binary numbers. We assume that we are given arrival times for all input bits and optimize the delay of the circuits, i.e.\ the time when the last output bit is computed. This contains the classical optimization of depth as a special case where all arrival times are $0$. In this model, we present, among other results, the fastest adder circuits of sub-quadratic size and the fastest adder circuits of linear size. In particular, for adding two $n$-numbers we get a circuits with linear size and delay $\log_2W+3\log_2\log_2n+4\log_2\log_2\log_2n +const$ where $\log_2W$ is a lower bound for the delay of any adder circuit (no matter what size it has).