Delay Balancing with Clock-Follow-Data: Optimizing Area Delay Trade-offs for Robust Rapid Single Flux Quantum Circuits

TL;DR

This paper introduces a novel algorithm for synthesizing clock-follow-data RSFQ circuits that balances delays and enhances robustness, significantly reducing area delay product compared to existing methods.

Contribution

The paper presents a new delay balancing algorithm for RSFQ circuits that improves robustness against timing violations while minimizing area and maintaining high performance.

Findings

Average 1.48x improvement in area delay product over full path balancing designs.

2.07x improvement in ADP over state-of-the-art multi-phase clocking solutions.

Algorithm effectively accounts for timing variations and adjusts clock bias and frequency.

Abstract

This paper proposes an algorithm for synthesis of clock-follow-data designs that provides robustness against timing violations for RSFQ circuits while maintaining high performance and minimizing area costs. Since superconducting logic gates must be clocked, managing data flow is a challenging problem that often requires the insertion of many path balancing D Flips (DFFs) to properly sequence data, leading to a substantial increase in area. To address this challenge, we present an algorithm to insert DFFs into clock-follow-data RSFQ circuits that partially balances the delays within the circuit to achieve a target throughput while minimizing area. Our algorithm can account for expected timing variations and, by adjusting the bias of the clock network and clock frequency, we can mitigate unexpected timing violations post-fabrication. Quantifying the benefits of our approach with a benchmark suite with nominal delays, our designs offer an average 1.48x improvement in area delay product (ADP) over high frequency full path balancing (FPB) designs and a 2.07x improvement in ADP over the state of the art robust circuits provided by state-of-the-art (SOTA) multi-phase clocking solutions.