A Hardware-Aware Gate Cutting Framework for Practical Quantum Circuit Knitting
Xiangyu Ren, Mengyu Zhang, Antonio Barbalace

TL;DR
This paper introduces a hardware-aware circuit knitting framework that optimizes quantum circuit partitioning by considering hardware constraints, significantly reducing circuit depth and improving fidelity for near-term quantum devices.
Contribution
It presents a novel circuit cutting scheme that jointly optimizes gate cuts and SWAP insertions using hardware topology, improving practicality over prior methods.
Findings
Reduced total subcircuit depth by up to 64%.
Enhanced relative fidelity up to 2.7 times.
Demonstrated effectiveness on several quantum algorithms.
Abstract
Circuit knitting emerges as a promising technique to overcome the limitation of the few physical qubits in near-term quantum hardware by cutting large quantum circuits into smaller subcircuits. Recent research in this area has been primarily oriented towards reducing subcircuit sampling overhead. Unfortunately, these works neglect hardware information during circuit cutting, thus posing significant challenges to the follow on stages. In fact, direct compilation and execution of these partitioned subcircuits yields low-fidelity results, highlighting the need for a more holistic optimization strategy. In this work, we propose a hardware-aware framework aiming to advance the practicability of circuit knitting. Drawing a contrast with prior methodologies, the presented framework designs a cutting scheme that concurrently optimizes the number of gate cuttings and SWAP insertions during…
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