Register Aggregation for Hardware Decompilation
Varun Rao, Zachary D. Sisco

TL;DR
This paper introduces a register aggregation method for hardware decompilation that effectively recovers memory elements and registers from gate-level netlists, enhancing reverse engineering capabilities.
Contribution
The paper presents a novel technique for aggregating flip-flops into registers and memory blocks, improving decompilation of sequential logic and memory elements.
Findings
Successfully recovers memory elements in all tested circuits.
Aggregates up to 2048 bits into a single memory block.
Outperforms existing methods in memory element recovery.
Abstract
Hardware decompilation reverses logic synthesis, converting a gate-level digital electronic design, or netlist, back up to hardware description language (HDL) code. Existing techniques decompile data-oriented features in netlists, like loops and modules, but struggle with sequential logic. In particular, they cannot decompile memory elements, which pose difficulty due to their deconstruction into individual bits and the feedback loops they form in the netlist. Recovering multi-bit registers and memory blocks from netlists would expand the applications of hardware decompilation, notably towards retargeting technologies (e.g. FPGAs to ASICs) and decompiling processor memories. We devise a method for register aggregation, to identify relationships between the data flip-flops in a netlist and group them into registers and memory blocks, resulting in HDL code that instantiates these memory…
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Physical Unclonable Functions (PUFs) and Hardware Security · Embedded Systems Design Techniques
