ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips

TL;DR

ResiLogic introduces a novel design framework that enhances chip resilience against various attacks by leveraging composability and diversity, enabling secure, redundant circuits without extra space or cost.

Contribution

The paper proposes ResiLogic, a new approach using diversity by composability to improve fault and intrusion resilience in chip design without additional redundancy.

Findings

ResiLogic improves resilience against distribution, zonal, and compound attacks by a factor of five.

Utilizes E-Graphs to generate diverse circuits under rewrite rules.

Enables design-time diversity without extra space or cost.

Abstract

A long-standing challenge is the design of chips resilient to faults and glitches. Both fine-grained gate diversity and coarse-grained modular redundancy have been used in the past. However, these approaches have not been well-studied under other threat models where some stakeholders in the supply chain are untrusted. Increasing digital sovereignty tensions raise concerns regarding the use of foreign off-the-shelf tools and IPs, or off-sourcing fabrication, driving research into the design of resilient chips under this threat model. This paper addresses a threat model considering three pertinent attacks to resilience: distribution, zonal, and compound attacks. To mitigate these attacks, we introduce the \texttt{ResiLogic} framework that exploits \textit{Diversity by Composability}: constructing diverse circuits composed of smaller diverse ones by design. This gives designer the capability to create circuits at design time without requiring extra redundancy in space or cost. Using this approach at different levels of granularity is shown to improve the resilience of circuit design in \texttt{ResiLogic} against the three considered attacks by a factor of five. Additionally, we also make a case to show how E-Graphs can be utilized to generate diverse circuits under given rewrite rules.