PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting

TL;DR

PatternPaint is a diffusion-based framework that generates legal VLSI layout patterns with limited data, using inpainting and few-shot fine-tuning, enabling scalable design in new technology nodes.

Contribution

The paper introduces PatternPaint, a novel diffusion-based layout pattern generation method that works effectively with minimal training data and includes a practical few-shot fine-tuning approach.

Findings

Successfully generates legal complex patterns in 2D metal interconnect designs.

Achieves high diversity scores in pattern generation.

Improves legality rate by 1.87X with few-shot fine-tuning.

Abstract

Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new technology nodes. However, existing training-based methods for layout pattern generation rely on large datasets. In practical scenarios, especially when developing a new technology node, obtaining such extensive layout data is challenging. Consequently, training models with large datasets becomes impractical, limiting the scalability and adaptability of prior approaches. To this end, we propose PatternPaint, a diffusion-based framework capable of generating legal patterns with limited design-rule-compliant training samples. PatternPaint simplifies complex layout pattern generation into a series of inpainting processes with a template-based denoising scheme. Furthermore, we perform few-shot finetuning on a pretrained image foundation model with only 20 design-rule-compliant samples. Experimental results show that using a sub-3nm technology node (Intel 18A), our model is the only one that can generate legal patterns in complex 2D metal interconnect design rule settings among all previous works and achieves a high diversity score. Additionally, our few-shot finetuning can boost the legality rate with 1.87X improvement compared to the original pretrained model. As a result, we demonstrate a production-ready approach for layout pattern generation in developing new technology nodes.