A Physical Layer Analysis of Entropy in Delay-Based PUFs Implemented on FPGAs

TL;DR

This paper analyzes the physical sources of entropy in delay-based FPGA PUFs by statistically characterizing delay variations in basic FPGA components, providing insights into their contribution to PUF randomness.

Contribution

It introduces a method to quantify delay variations in FPGA components, enhancing understanding of the entropy sources in delay-based PUFs.

Findings

LUTs and nodes contribute significantly to delay variation

Statistical techniques effectively estimate component-level delay variations

Analysis of 50,015 measurements across 20 FPGAs reveals key entropy sources

Abstract

Physical Unclonable Functions (PUFs) leverage signal variations that occur within the device as a source of entropy. On-chip instrumentation is utilized by some PUF architectures to measure and digitize these variations, which are then processed into bitstrings and secret keys for use in security functions such as authentication and encryption. In many cases, the variations in the measured signals are introduced by a sequence of components in the circuit structure defined by the PUF architecture. In particular, the Hardware-Embedded deLay PUF (HELP) measures delay variations that occur in combinational logic paths on Field Programmable Gate Arrays (FPGAs), which are composed of a set of interconnecting wires (nodes) and look-up tables (LUTs). Previous investigations of variations in these path delays show that it is possible to derive high quality bitstrings, i.e., those which exhibit high levels of uniqueness and randomness across the device population. However, the underlying source and level of variations associated with the constituent components of the paths remain unknown. In this paper, we apply statistical averaging and differencing techniques to derive estimates for the delay variation associated with an FPGA's basic components, namely LUTs and nodes, as a means of fully characterizing the PUF's source of entropy. The analysis is carried out on a set of 50,015 path delay measurements collected from a set of 20 Xilinx Zynq 7020 SoC-class FPGAs, on which 25 identical instances of a functional unit are instantiated, for a total of 500 instances.