PC-Indexed Data Address Translation
Shyam Murthy, Gurindar S Sohi

TL;DR
This paper introduces PCAX, a method that uses the program counter of load instructions to improve data address translation efficiency, significantly reducing TLB misses and enhancing performance.
Contribution
It presents a novel approach that leverages static load instruction PC to assist data address translation, reducing miss rates and improving performance.
Findings
Effective miss rate of DTLB reduced by 2-3X in many cases
Reduces secondary TLB misses
Average performance improvement of 1.7% with 7% energy savings
Abstract
This paper proposes a novel way to assist conventional data address translation. The approach, PC-Indexed Data Address Translation (PCAX), uses the PC of a load instruction, and not a data virtual address, to obtain the page table entry (PTE) for the data accessed by a load instruction. PCAX is intended to be used for a small subset of the static loads in a program. We observe that: (i) a small subset of static loads is responsible for most of the misses in a data translation lookaside buffer (DTLB), and (ii) often a dynamic instance of a static load instruction accesses the same PTE as the last dynamic instance, and consider PCAX for this subset. With PCAX the effective miss rate of a conventional DTLB can be cut down by a factor of 2-3X in many cases, and even more in some cases. PCAX is also beneficial in reducing the number of secondary TLB (STLB) misses. Since the tables used for…
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