Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM
Ahmed Mamdouh, Haoran Geng, Michael Niemier, Xiaobo Sharon Hu, and, Dayane Reis

TL;DR
Shared-PIM is a novel in-DRAM architecture that enables concurrent computation and data flow, significantly reducing latency and energy consumption while boosting performance for various data-intensive tasks.
Contribution
It introduces a memory bank allocation strategy for concurrent processing and data movement, improving upon existing architectures like LISA and pLUTo.
Findings
Reduces data movement latency by 5x and energy by 1.2x compared to LISA.
Achieves 1.4x faster arithmetic operations and 40-44% performance improvements in matrix and polynomial multiplication.
Provides a 29% speedup in graph processing tasks with 7.16% area overhead.
Abstract
Processing-in-Memory (PIM) enhances memory with computational capabilities, potentially solving energy and latency issues associated with data transfer between memory and processors. However, managing concurrent computation and data flow within the PIM architecture incurs significant latency and energy penalty for applications. This paper introduces Shared-PIM, an architecture for in-DRAM PIM that strategically allocates rows in memory banks, bolstered by memory peripherals, for concurrent processing and data movement. Shared-PIM enables simultaneous computation and data transfer within a memory bank. When compared to LISA, a state-of-the-art architecture that facilitates data transfers for in-DRAM PIM, Shared-PIM reduces data movement latency and energy by 5x and 1.2x respectively. Furthermore, when integrated to a state-of-the-art (SOTA) in-DRAM PIM architecture (pLUTo), Shared-PIM…
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Taxonomy
TopicsAdvanced Data Storage Technologies · Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices
