HAPM -- Hardware Aware Pruning Method for CNN hardware accelerators in resource constrained devices

TL;DR

This paper introduces a hardware-aware pruning method for CNNs tailored for FPGA accelerators, significantly improving inference speed in resource-constrained devices by exploiting sparsity and hardware scheduling.

Contribution

The work presents a generic FPGA-compatible hardware architecture and a custom pruning algorithm optimized for this hardware, outperforming standard pruning in inference speed.

Findings

Hardware-aware pruning achieves 45% faster inference.

Proposed architecture supports multiple CNN configurations.

Custom pruning exploits hardware scheduling for efficiency.

Abstract

During the last years, algorithms known as Convolutional Neural Networks (CNNs) had become increasingly popular, expanding its application range to several areas. In particular, the image processing field has experienced a remarkable advance thanks to this algorithms. In IoT, a wide research field aims to develop hardware capable of execute them at the lowest possible energy cost, but keeping acceptable image inference time. One can get around this apparently conflicting objectives by applying design and training techniques. The present work proposes a generic hardware architecture ready to be implemented on FPGA devices, supporting a wide range of configurations which allows the system to run different neural network architectures, dynamically exploiting the sparsity caused by pruning techniques in the mathematical operations present in this kind of algorithms. The inference speed of the design is evaluated over different resource constrained FPGA devices. Finally, the standard pruning algorithm is compared against a custom pruning technique specifically designed to exploit the scheduling properties of this hardware accelerator. We demonstrate that our hardware-aware pruning algorithm achieves a remarkable improvement of a 45 % in inference time compared to a network pruned using the standard algorithm.