When In-memory Computing Meets Spiking Neural Networks -- A Perspective on Device-Circuit-System-and-Algorithm Co-design

TL;DR

This paper reviews the integration of Spiking Neural Networks with In-Memory Computing, emphasizing device, circuit, and system co-design for low-power neuromorphic edge computing solutions.

Contribution

It provides a comprehensive analysis of the synergies and challenges in co-designing SNNs with IMC architectures across device, circuit, and system levels.

Findings

Identification of system-level bottlenecks due to device limitations

Highlighting the importance of algorithm-hardware co-design for performance optimization

Emphasizing holistic design space exploration for neuromorphic systems

Abstract

This review explores the intersection of bio-plausible artificial intelligence in the form of Spiking Neural Networks (SNNs) with the analog In-Memory Computing (IMC) domain, highlighting their collective potential for low-power edge computing environments. Through detailed investigation at the device, circuit, and system levels, we highlight the pivotal synergies between SNNs and IMC architectures. Additionally, we emphasize the critical need for comprehensive system-level analyses, considering the inter-dependencies between algorithms, devices, circuit & system parameters, crucial for optimal performance. An in-depth analysis leads to identification of key system-level bottlenecks arising from device limitations which can be addressed using SNN-specific algorithm-hardware co-design techniques. This review underscores the imperative for holistic device to system design space co-exploration, highlighting the critical aspects of hardware and algorithm research endeavors for low-power neuromorphic solutions.