In-Memory Computing Architecture for Efficient Hardware Security
Hala Ajmi, Fakhreddine Zayer, Hamdi Belgacem

TL;DR
This paper introduces an in-memory computing architecture using memristors for efficient AES encryption, significantly improving power efficiency and throughput, enhancing security for IoT and autonomous systems.
Contribution
It develops a novel memristor-based in-memory computing architecture for AES, achieving substantial improvements in power and throughput over traditional hardware.
Findings
30% power reduction compared to traditional AES hardware
62% throughput improvement over recent AES NVM engines
Enhanced security for IoT and autonomous systems
Abstract
This paper presents an innovative approach utilizing in-memory computing (IMC) for the development and integration of AES (Advanced Encryption Standard) cipher technique. Our research aims to enhance cybersecurity measures for a wide range of applications for IoT, such as robotic self-driving and several uses contexts. Memristor (MR) design optimized for in-memory processing is introduced. Our work highlights the development of a 4-bit state memristor device tailored for various range of arithmetic functions in a hardware prototype of AES system. Additionally, we propose a pipeline AES design aimed at harnessing extensive parallelism and ensuring compatibility with MR devices. This approach enhances hardware performance by by managing larger data amounts, accelerating computational, and achieving greater precision demands. Compared to traditional AES hardware, AES-IMC demonstrates an…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Memory and Neural Computing · Security and Verification in Computing
