Optimizing Quantum Fourier Transformation (QFT) Kernels for Modern NISQ and FT Architectures

TL;DR

This paper introduces a novel domain-specific approach to optimize Quantum Fourier Transformation circuits for NISQ architectures, significantly reducing gate count and circuit depth compared to existing methods.

Contribution

It presents the first guaranteed linear-depth QFT circuit synthesis method for multiple hardware architectures using program synthesis tools.

Findings

Up to 53% reduction in SWAP gates

Up to 92% reduction in circuit depth

Guarantees linear-depth circuits for various hardware architectures

Abstract

Rapid development in quantum computing leads to the appearance of several quantum applications. Quantum Fourier Transformation (QFT) sits at the heart of many of these applications. Existing work leverages SAT solver or heuristics to generate a hardware-compliant circuit for QFT by inserting SWAP gates to remap logical qubits to physical qubits. However, they might face problems such as long compilation time due to the huge search space for SAT solver or suboptimal outcome in terms of the number of cycles to finish all gate operations. In this paper, we propose a domain-specific hardware mapping approach for QFT. We unify our insight of relaxed ordering and unit exploration in QFT to search for a qubit mapping solution with the help of program synthesis tools. Our method is the first one that guarantees linear-depth QFT circuits for Google Sycamore, IBM heavy-hex, and the lattice surgery, with respect to the number of qubits. Compared with state-of-the-art approaches, our method can save up to 53% in SWAP gate and 92% in depth.