Design and Implementation of a Takum Arithmetic Hardware Codec

TL;DR

This paper introduces a hardware codec for takum numbers, a novel number format with enhanced precision and dynamic range, demonstrating significant performance improvements over existing posit codecs on FPGA.

Contribution

It presents the design and implementation of a takum hardware codec, including a new internal representation and optimizations for FPGA performance.

Findings

Achieves up to 38% latency reduction

Reduces LUT utilization by up to 50%

Demonstrates near-optimal scalability and performance

Abstract

The takum machine number format has been recently proposed as an enhancement over the posit number format, which is considered a promising alternative to the IEEE 754 floating-point standard. Takums retain the useful posit properties, but feature a novel exponent coding scheme that yields more precision for small and large magnitude numbers and a much higher and bounded dynamic range. This paper presents the design and implementation of a hardware codec for both takums (logarithmic number system, LNS) and linear takums (floating-point format). The codec design is emphasised, as it constitutes the primary distinguishing feature compared to logarithmic posits (LNS) and posits (floating-point format), which otherwise share similar internal representations. Furthermore, a novel internal representation for LNS is proposed. The presented takum codec, implemented in VHDL, demonstrates near-optimal scalability and performance on an FPGA. It achieves latency reductions of up to 38% and reduces LUT utilisation up to 50% compared to the best state-of-the-art posit codecs.