Are LLMs Any Good for High-Level Synthesis?

TL;DR

This paper investigates the potential of Large Language Models to improve High-Level Synthesis by comparing their generated hardware designs with traditional tools, focusing on performance, power, and resource efficiency.

Contribution

It provides a comprehensive survey and experimental analysis of LLM-based approaches for HLS, highlighting their capabilities and limitations compared to standard methods.

Findings

LLMs can generate Verilog code from natural language specifications.

LLM-based designs show comparable performance to traditional HLS in some cases.

Resource utilization varies significantly depending on the LLM approach.

Abstract

The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.