FPCA: Field-Programmable Pixel Convolutional Array for Extreme-Edge Intelligence

TL;DR

This paper introduces FPCA, a reconfigurable, scalable, and efficient field-programmable pixel array architecture for neural network acceleration at the extreme-edge, integrating non-volatile memory for dynamic adaptability.

Contribution

The work presents a novel pixel circuit design with integrated NVM enabling reconfigurable convolutional neural network processing, improving flexibility and scalability over static existing solutions.

Findings

Demonstrates dot product operation capabilities of the circuit.

Shows non-linearity in analog output and models it with a bucket-select curvefit.

Achieves significant area reduction per pixel, enhancing density and scalability.

Abstract

The rapid advancement of neural network applications necessitates hardware that not only accelerates computation but also adapts efficiently to dynamic processing requirements. While processing-in-pixel has emerged as a promising solution to overcome the bottlenecks of traditional architectures at the extreme-edge, existing implementations face limitations in reconfigurability and scalability due to their static nature and inefficient area usage. Addressing these challenges, we present a novel architecture that significantly enhances the capabilities of processing-in-pixel for convolutional neural networks. Our design innovatively integrates non-volatile memory (NVM) with novel unit pixel circuit design, enabling dynamic reconfiguration of synaptic weights, kernel size, channel size and stride size. Thus offering unprecedented flexibility and adaptability. With using a separate die for pixel circuit and storing synaptic weights, our circuit achieves a substantial reduction in the required area per pixel thereby increasing the density and scalability of the pixel array. Simulation results demonstrate dot product operations of the circuit, the non-linearity of its analog output and a novel bucket-select curvefit model is proposed to capture it. This work not only addresses the limitations of current in-pixel computing approaches but also opens new avenues for developing more efficient, flexible, and scalable neural network hardware, paving the way for advanced AI applications.