In-Memory Learning Automata Architecture using Y-Flash Cell

TL;DR

This paper presents a novel in-memory computing architecture using Y-Flash memristive devices to implement Tsetlin Machine automata, enabling scalable and efficient edge learning with reduced data transfer bottlenecks.

Contribution

It introduces a new hardware implementation of Tsetlin Machine automata using Y-Flash memristors, combining analog tunability with CMOS compatibility for improved in-memory learning.

Findings

Demonstrated enhanced scalability of the proposed architecture

Showed reliable decision-making with moderate device variation

Simulated effective in-memory processing for edge ML applications

Abstract

The modern implementation of machine learning architectures faces significant challenges due to frequent data transfer between memory and processing units. In-memory computing, primarily through memristor-based analog computing, offers a promising solution to overcome this von Neumann bottleneck. In this technology, data processing and storage are located inside the memory. Here, we introduce a novel approach that utilizes floating-gate Y-Flash memristive devices manufactured with a standard 180 nm CMOS process. These devices offer attractive features, including analog tunability and moderate device-to-device variation; such characteristics are essential for reliable decision-making in ML applications. This paper uses a new machine learning algorithm, the Tsetlin Machine (TM), for in-memory processing architecture. The TM's learning element, Automaton, is mapped into a single Y-Flash cell, where the Automaton's range is transferred into the Y-Flash's conductance scope. Through comprehensive simulations, the proposed hardware implementation of the learning automata, particularly for Tsetlin machines, has demonstrated enhanced scalability and on-edge learning capabilities.