VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

TL;DR

VerilogCoder is an AI-driven system that autonomously generates and corrects Verilog hardware description code using graph-based planning and AST-based waveform tracing, significantly improving accuracy over existing methods.

Contribution

It introduces a novel task planner with a Task and Circuit Relation Graph retrieval method and an AST-based waveform tracing tool for error debugging in Verilog code.

Findings

Achieves 94.2% syntactic and functional correctness in Verilog code generation.

Surpasses state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.

Integrates AI agents with Verilog tools for autonomous hardware design.

Abstract

Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using collaborative Verilog tools (i.e., syntax checker, simulator, and waveform tracer). Firstly, we propose a task planner that utilizes a novel Task and Circuit Relation Graph retrieval method to construct a holistic plan based on module descriptions. To debug and fix functional errors, we develop a novel and efficient abstract syntax tree (AST)-based waveform tracing tool, which is integrated within the autonomous Verilog completion flow. The proposed methodology successfully generates 94.2% syntactically and functionally correct Verilog code, surpassing the state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.