A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR

TL;DR

This paper presents an open-source, high-performance RISC-V based architecture for 6G baseband processing, featuring 1024 cores, high bandwidth memory, and low latency, achieving state-of-the-art energy efficiency.

Contribution

It introduces a scalable, low-latency RISC-V core cluster with high bandwidth memory integration for next-generation wireless baseband processing.

Findings

Achieves 98% peak bandwidth with HBM2E (910GBps)

Attains high energy efficiency in key 6G kernels (up to 125 GOPS/W)

Maintains sub-millisecond latency with minimal data movement overhead

Abstract

We introduce an open-source architecture for next-generation Radio-Access Network baseband processing: 1024 latency-tolerant 32-bit RISC-V cores share 4 MiB of L1 memory via an ultra-low latency interconnect (7-11 cycles), a modular Direct Memory Access engine provides an efficient link to a high bandwidth memory, such as HBM2E (98% peak bandwidth at 910GBps). The system achieves leading-edge energy efficiency at sub-ms latency in key 6G baseband processing kernels: Fast Fourier Transform (93 GOPS/W), Beamforming (125 GOPS/W), Channel Estimation (96 GOPS/W), and Linear System Inversion (61 GOPS/W), with only 9% data movement overhead.