Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

TL;DR

This paper presents PigMAP, a novel framework that guides technology mapping with primitive gate placement to optimize wirelength, delay, and power in VLSI design, reducing iterations between synthesis and physical design stages.

Contribution

PigMAP introduces a spatially aware, wirelength-driven mapping algorithm with dual modes for performance and power optimization, enhancing physical design integration.

Findings

Performance mode reduces delay by 14%.

Power mode reduces power consumption by 9%.

Both modes improve design metrics with minimal trade-offs.

Abstract

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption.