Hardware Architecture Design of Model-Based Image Reconstruction Towards Palm-size Photoacoustic Tomography

TL;DR

This paper presents a hardware architecture for palm-size photoacoustic tomography that significantly accelerates image reconstruction, reduces system cost, and maintains high image quality, enabling portable and efficient biomedical imaging.

Contribution

The paper introduces a novel hardware architecture based on s-Wave for palm-PAT, featuring a data reuse method that lowers hardware resource use and achieves substantial speed and energy efficiency improvements.

Findings

FPGA implementation demonstrates 270x speedup over CPU.

Energy efficiency improved by over 2700 times.

Maintains high imaging quality with reduced hardware cost.

Abstract

Photoacoustic (PA) imaging technology combines the advantages of optical imaging and ultrasound imaging, showing great potential in biomedical applications. Many preclinical studies and clinical applications urgently require fast, high-quality, low-cost and portable imaging system. Translating advanced image reconstruction algorithms into hardware implementations is highly desired. However, existing iterative PA image reconstructions, although exhibit higher accuracy than delay-and-sum algorithm, suffer from high computational cost. In this paper, we introduce a model-based hardware acceleration architecture based on superposed Wave (s-Wave) for palm-size PA tomography (palm-PAT), aiming at enhancing both the speed and performance of image reconstruction at a much lower system cost. To achieve this, we propose an innovative data reuse method that significantly reduces hardware storage resource consumption. We conducted experiments by FPGA implementation of the algorithm, using both phantoms and in vivo human finger data to verify the feasibility of the proposed method. The results demonstrate that our proposed architecture can substantially reduce system cost while maintaining high imaging performance. The hardware-accelerated implementation of the model-based algorithm achieves a speedup of up to approximately 270 times compared to the CPU, while the corresponding energy efficiency ratio is improved by more than 2700 times.