Quantum Annealing based Power Grid Partitioning for Parallel Simulation

TL;DR

This paper explores using quantum annealing to optimize power grid partitioning for parallel simulation, demonstrating a QUBO formulation tested on D-Wave hardware, highlighting current limitations and future potential.

Contribution

It introduces a novel QUBO formulation for power grid partitioning optimized via quantum annealing and evaluates its feasibility on current quantum hardware.

Findings

QUBO formulation successfully maps partitioning problem

Current hardware limits problem size to under 200 buses

Embedding process impacts time-to-solution

Abstract

Graph partitioning has many applications in powersystems from decentralized state estimation to parallel simulation. Focusing on parallel simulation, optimal grid partitioning minimizes the idle time caused by different simulation times for the sub-networks and their components and reduces the overhead required to simulate the cuts. Partitioning a graph into two parts such that, for example, the cut is minimal and the subgraphs have equal size is an NP-hard problem. In this paper we show how optimal partitioning of a graph can be obtained using quantum annealing (QA). We show how to map the requirements for optimal splitting to a quadratic unconstrained binary optimization (QUBO) formulation and test the proposed formulation using a current D-Wave QPU. We show that the necessity to find an embedding of the QUBO on current D-Wave QPUs limits the problem size to under 200 buses and notably affects the time-to-solution. We finally discuss the implications on near-term implementation of QA in combination to traditional CPU or GPU based simulation.