Left of Fab: Securing Design and Collaboration in the Semiconductor Value Chain

TL;DR

This paper analyzes the security challenges in semiconductor design workflows, comparing them to PCB processes, and proposes a framework to secure these workflows amid increasing industry and geopolitical pressures.

Contribution

It introduces a vendor- and tool-agnostic framework for understanding and securing integrated circuit design workflows, addressing a significant knowledge gap.

Findings

Comparison of IC and PCB design workflows

Classification of security threats in semiconductor design

Framework for securing design workflows

Abstract

The purpose of this paper is to fill a gap in the general understanding -- and academic scrutiny -- of current and emerging workflows for designing and fabricating integrated circuits. The approach is to compare the IC design workflow with that for printed circuit boards, then to discern a classification for threats. The need to define and secure workflows is amplified by both U.S. investment in the semiconductor manufacturing and market forces affecting GPU production for AI applications. The origin of this knowledge gap can be the proprietary nature of solution spaces, but it can be the lack of demand for teaching and learning for engineers and technicians in this domain. This paper presents a framework for understanding the security of design workflows in a vendor- and tool-agnostic way.