Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools

TL;DR

This paper demonstrates implementing the Finite-Time Lyapunov Exponent calculation on FPGA using High-Level Synthesis tools, showing performance and resource usage for 2D and 3D cases.

Contribution

It presents a novel FPGA implementation of FTLE calculation using HLS, highlighting performance gains and resource efficiency.

Findings

Speed improvements over CPU implementations

Resource consumption analysis for 2D and 3D cases

Feasibility of FPGA acceleration for fluid dynamics applications

Abstract

As Field Programmable Gate Arrays (FPGAs) computing capabilities continue to grow, also does the interest on building scientific accelerators around them. Tools like Xilinx's High-Level Synthesis (HLS) help to bridge the gap between traditional high-level languages such as C and C++, and low-level hardware description languages such as VHDL and Verilog. In this report, we study the implementation of a fluid dynamics application, the Finite-Time Lyapunov Exponent (FTLE) calculation, on FPGA using HLS. We provide speed and resource-consumption results for 2- and 3-dimensional cases.